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integrated mixed-signal solutions preliminary data sheet stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output data sheet revision 6.0 not recommended for new designs. please use the stac9766/67 cc1 and beyond. documentation available at www.sigmatel.com. two-channel ac?97 codecs with headphone drive and spdif out- put not recommended for new designs - 8/2/02 2-9766-d1-6.0-0802
2 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 1. table of contents 1. table of contents .......................................................................................................... ... 2 1.1. list of figures .......................................................................................................... ..........................4 1.2. list of tables ........................................................................................................... ...........................5 2. product brief .............................................................................................................. ........ 6 2.1. features ................................................................................................................. ............................6 2.2. description .............................................................................................................. ...........................6 2.3. ordering information ..................................................................................................... .....................7 2.4. stac9766/67 block diagram ............................................................................................... ............8 2.5. key specifications ....................................................................................................... .......................8 2.6. related materials ........................................................................................................ .......................8 2.7. additional support ....................................................................................................... .......................8 3. characteristics/specifications .................................................................................. 9 3.1. electrical specifications ................................................................................................ .....................9 3.1.1. absolute maximum ratings: .............................................................................................. ..9 3.1.2. recommended operating conditions .................................................................................9 3.1.3. power consumption ..................................................................................................... .......9 3.1.4. ac-link static digital specifications .................................................................................. 10 3.1.5. stac9766 analog performance characteristics ...............................................................10 3.1.6. stac9767 analog performance characteristics ...............................................................11 3.2. ac timing characteristics ................................................................................................ ...............13 3.2.1. cold reset ............................................................................................................. ............13 3.2.2. warm reset ............................................................................................................. ..........13 3.2.3. clocks ................................................................................................................. ...............14 3.2.4. data setup and hold .................................................................................................... ......15 3.2.5. signal rise and fall times ............................................................................................. ...15 3.2.6. ac-link low power mode timing ......................................................................................16 3.2.7. ate test mode .......................................................................................................... ........16 4. typical connection diagram .......................................................................................17 5. ac-link .................................................................................................................... ...............18 5.1. clocking ................................................................................................................. ..........................18 5.2. reset .................................................................................................................... ............................18 6. digital interface .......................................................................................................... ....19 6.1. ac-link digital serial interface protocol ................................................................................ ..........19 6.1.1. ac-link audio output frame (sdata_out) ....................................................................20 6.1.1.1. slot 1: command address port ........................................................................21 6.1.1.2. slot 2: command data port ..............................................................................21 6.1.1.3. slot 3: pcm playback left channel ..................................................................21 6.1.1.4. slot 4: pcm playback right channel ...............................................................21 6.1.1.5. slot 5: reserved ...............................................................................................22 6.1.1.6. slot 6: pcm center channel ............................................................................22 6.1.1.7. slot 7: pcm left surround channel .................................................................22 6.1.1.8. slot 8: pcm right surround channel ...............................................................22 6.1.1.9. slot 9: pcm low frequency channel ...............................................................22 6.1.1.10. slot 10: pcm alternate left ............................................................................22 6.1.1.11. slot 11: pcm alternate right ..........................................................................22 copyright ? 2001 sigmatel, inc. all rights reserved. all contents of this document are protected by copyright law and may not be reproduced without the express written consent of s igmatel, inc. sigmatel, the sigmatel logo, and combinations thereof are trademarks of sigmatel, inc. other product names used in this publica tion are for identification purposes only and may be trademarks or registered trademarks of their respective companies. the contents of this document are provided in connection with sigmatel, inc. products. sigmatel, inc. has made best efforts to ensure that the infor mation contained herein is accurate and reliable. however, sigmatel, inc. makes no warranties, express or implied, as to the accuracy or com- pleteness of the contents of this publication and is providing this publication ?as is?. sigmatel, inc. reserves the right to m ake changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at an y time without notice. sigmatel, inc. does not assume any liability arising out of the application or use of any product or circuit, and speci fically disclaims any and all liability, including without limitation special, consequential, or incidental damages.
2-9766-d1-6.0-0802 3 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.1.12. slot 12: reserved ...........................................................................................22 6.1.2. ac-link audio input frame (sdata_in) ...........................................................................23 6.1.2.1. slot 1: status address port ...............................................................................24 6.1.2.2. slot 2: status data port ....................................................................................24 6.1.2.3. slot 3: pcm record left channel .....................................................................24 6.1.2.4. slot 4: pcm record right channel ..................................................................25 6.1.2.5. slot 5: reserved ...............................................................................................25 6.1.2.6. slot 6: pcm left record channel ....................................................................25 6.1.2.7. slot 7: pcm left record channel ....................................................................25 6.1.2.8. slot 8: pcm right record channel .................................................................25 6.1.2.9. slot 9: pcm right record channel .................................................................25 6.1.2.10. slot 10: pcm left record channel ................................................................26 6.1.2.11. slot 11: pcm right record channel .............................................................26 6.1.2.12. slot 12: reserved ..........................................................................................26 6.2. ac-link low power mode ................................................................................................... ............26 6.3. waking up the ac-link .................................................................................................... ................27 7. stac9766/67 mixer .......................................................................................................... ....28 7.1. analog mixer input ....................................................................................................... ....................30 7.2. analog mixer output ...................................................................................................... ..................30 7.3. spdif digital mux ........................................................................................................ ....................30 7.4. pc beep implementation ................................................................................................... ..............30 7.5. programming registers .................................................................................................... ...............31 7.5.1. reset (00h) ............................................................................................................ ............32 7.5.2. play master volume registers (index 02h, 04h, and 06h) .................................................32 7.5.2.1. master volume (02h) ........................................................................................32 7.5.2.2. headphone out volume (04h) ..........................................................................32 7.5.2.3. master volume mono (06h) ............................................................................33 7.5.3. pc beep mixer volume (index 0ah) ..................................................................................33 7.5.4. analog mixer input gain registers (index 0ch - 18h) .......................................................34 7.5.4.1. phone mixer volume (0ch) ..............................................................................34 7.5.4.2. mic mixer volume (0eh) ...................................................................................34 7.5.4.3. line in mixer volume (10h) ...............................................................................34 7.5.4.4. cd mixer volume (12h) ....................................................................................34 7.5.4.5. video mixer volume (14h) ................................................................................35 7.5.4.6. aux mixer volume (16h) ..................................................................................35 7.5.4.7. pcm out mixer volume (18h) ...........................................................................35 7.5.5. record select (1ah) .................................................................................................... .......36 7.5.6. record gain (1ch) ...................................................................................................... .......36 7.5.7. general purpose (20h) .................................................................................................. .....37 7.5.8. 3d control (22h) ....................................................................................................... ..........37 7.5.9. powerdown ctrl/stat (26h) .............................................................................................. ...38 7.5.9.1. ready status ....................................................................................................38 7.5.9.2. powerdown controls .........................................................................................38 7.5.9.3. external amplifier power down control ............................................................38 7.5.10. extended audio id (28h) ............................................................................................... ...39 7.5.11. extended audio control/status (2ah) ..............................................................................40 7.5.11.1. variable rate sampling enable ......................................................................40 7.5.11.2. spdif .............................................................................................................40 7.5.11.3. spcv (spdif configuration valid) .................................................................40 7.5.11.4. spsa1, spsa0 (spdif slot assignment) ......................................................41 7.5.12. pcm dac rate registers (2ch and 32h) ........................................................................41 7.5.13. pcm dac rate (2ch) .................................................................................................... ..42 7.5.14. pcm lr adc rate (32h) ................................................................................................. 42 7.5.15. spdif control (3ah) ................................................................................................... .....42 7.5.16. digital audio control (6ah) ........................................................................................... ....43 7.5.17. revision code (6ch) ................................................................................................... .....44 7.5.18. analog special (6eh) .................................................................................................. .....44 7.5.18.1. all mix ..........................................................................................................44
4 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.18.2. adc data on ac link ....................................................................................45 7.5.18.3. mic boost select .............................................................................................45 7.5.18.4. supply override select ...................................................................................45 7.5.18.5. 72h enable (70h) ............................................................................................45 7.5.18.6. analog current adjust (72h) ...........................................................................45 7.5.18.7. internal power-on/off anti-pop circuit ...........................................................46 7.5.19. gpio access register (74h) ............................................................................................ 46 7.5.20. high pass filter bypass (index 76h and 78h) ..................................................................47 7.5.20.1. 78h enable (76h) ............................................................................................47 7.5.20.2. adc high pass filter bypass(78h) ................................................................47 7.5.21. vendor id1 and id2 (index 7ch and 7eh) .......................................................................47 7.5.21.1. vendor id1 (7ch) ............................................................................................48 7.5.21.2. vendor id2 7666 (7eh) ...................................................................................48 8. low power modes ............................................................................................................ 49 9. multiple codec support ...............................................................................................51 9.1. primary/secondary codec selection ........................................................................................ .......51 9.1.1. primary codec operation ................................................................................................ ...51 9.1.2. secondary codec operation .............................................................................................. 51 9.2. secondary codec register access definitions .............................................................................. ..52 10. testability ............................................................................................................... .........53 11. pin description ........................................................................................................... .....54 11.1. digital i/o ............................................................................................................. ..........................55 11.2. analog i/o .............................................................................................................. ........................56 11.3. filter/references/gpio .................................................................................................. ................57 11.4. power and ground signals ................................................................................................ ............57 12. package drawing .......................................................................................................... 58 13. appendix a: split independent power supply operation ..............................59 14. appendix b: programming registers .....................................................................61 1.1. list of figures figure 1. stac9766/67 block diagram ........................................................................................... ................8 figure 2. cold reset timing ................................................................................................... .......................13 figure 3. warm reset timing ................................................................................................... .....................13 figure 4. clocks timing ....................................................................................................... ..........................14 figure 5. data setup and hold timing .......................................................................................... .................15 figure 6. signal rise and fall times timing ................................................................................... ...............15 figure 7. ac-link low power mode timing ....................................................................................... ............16 figure 8. ate test mode timing ................................................................................................ ...................16 figure 9. stac9767 typical connection diagram ................................................................................. .......17 figure 10. ac-link to its companion controller ................................................................................ .............18 figure 11. ac?97 standard bi-directional audio frame .......................................................................... .......19 figure 12. ac-link audio output frame ......................................................................................... ...............20 figure 13. start of an audio output frame ..................................................................................... ...............20 figure 14. stac9766/67 audio input frame ...................................................................................... ...........23 figure 15. start of an audio input frame ...................................................................................... .................24 figure 16. stac9766/67 powerdown timing ....................................................................................... .........26 figure 17. stac9766 2-channel mixer functional diagram ........................................................................ .29 figure 18. stac9767 2-channel mixer functional diagram ........................................................................ .29 figure 19. example of stac9766/67 powerdown/powerup flow ..................................................................49 figure 20. stac9766/67 powerdown/powerup flow with analog still alive ...................................................50 figure 21. stac9766/67 pin description drawing ................................................................................ ........54 figure 22. 48-pin tqfp package drawing ........................................................................................ ............58 figure 23. stac9766/67 split independent power supply operation typical connection diagram ............60
2-9766-d1-6.0-0802 5 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 1.2. list of tables table 1. recommended operating conditions. .................................................................................... ...........9 table 2. power consumption .................................................................................................... .......................9 table 3. ac-link static specifications ........................................................................................ ...................10 table 4. stac9766 analog performance characteristics .......................................................................... ...10 table 5. stac9767 analog performance characteristics .......................................................................... ...11 table 6. cold reset specifications ............................................................................................ ....................13 table 7. warm reset specifications ............................................................................................ ..................13 table 8. clocks specifications ................................................................................................ .......................14 table 9. clock mode configuration ............................................................................................. ....................14 table 10. data setup and hold specifications .................................................................................. .............15 table 11. signal rise and fall times specifications ........................................................................... ..........15 table 12. ac-link low power mode timing specifications ........................................................................ ...16 table 13. ate test mode specifications ........................................................................................ ...............16 table 14. stac9766/67 available data streams .................................................................................. ........19 table 15. command address port bit assignments ................................................................................ ......21 table 16. command data port bit assignments ................................................................................... .........21 table 17. status address port bit assignments ................................................................................. ............24 table 18. status data port bit assignments .................................................................................... ..............24 table 19. programming registers ............................................................................................... ...................31 table 20. play master volume register ......................................................................................... ................32 table 21. pc_beep register .................................................................................................... ....................33 table 22. analog mixer input gain register .................................................................................... ..............34 table 23. record select control registers ..................................................................................... ...............36 table 24. record gain registers .............................................................................................. ....................36 table 25. general purpose register ............................................................................................ ..................37 table 26. 3d control registers ............................................................................................... ......................37 table 27. powerdown status registers .......................................................................................... ...............38 table 28. extended audio id ................................................................................................... ......................39 table 29. slot assignment relationship between spsa1 and spsa0 ............................................................41 table 30. stac9766/67 amap compliant .......................................................................................... ...........41 table 31. hardware supported sample rates ..................................................................................... ..........41 table 32. spdif control ....................................................................................................... .........................42 table 33. digital audio control register ...................................................................................... ..................43 table 34. adc data on ac link ................................................................................................. ...................45 table 35. mic boost select .................................................................................................... ........................45 table 37. gpio access registers (74h) ......................................................................................... ...............46 table 36. analog current adjust ............................................................................................... .....................46 table 38. low power modes ..................................................................................................... .....................49 table 39. codec id selection .................................................................................................. ......................51 table 40. secondary codec register access slot 0 bit definitions .............................................................. .52 table 41. digital connection signals .......................................................................................... ...................55 table 42. analog connection signals ........................................................................................... .................56 table 43. filtering and voltage references .................................................................................... ...............57 table 44. power and ground signals ............................................................................................ ................57 table 45. 48-pin tqfp package dimensions ...................................................................................... ..........58
6 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 2. product brief 2.1. features full duplex stereo 18-bit adc and 20-bit dac ac ? 97 rev 2.2-compliant high performance ? technology spdif output crystal elimination circuit headphone amplifier independent sample rates for adc & dacs (hardware srcs) 20 or 30 db microphone boost capability 103 db snr line-line 5-wire ac-link protocol compliance digital-ready architecture general purpose i/o +3.3v (stac9767) and +5v (stac9766) analog power supply options pin compatible with the stac9700/21/44/08/56 sigmatel surround (ss3d) stereo enhancement energy saving dynamic power modes 2.2. description sigmatel's stac9766/67 are general purpose 18-bit adc, 20-bit dac, full duplex, audio codecs conforming to the analog component specification of ac'97 (audio codec 97 component specification rev. 2.2). the stac9766/67 incorporate sig- matel's proprietary ? technology to achieve a dac snr in excess of 95 db. the dacs, adcs, and mixer are integrated with analog i/os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. the stac9766/67 include digital input/output capability for support of modern pc systems with an output that supports the spdif format. the stac9766/67 is a standard 2-channel stereo codec. with sigmatel ? s head- phone drive capability, headphones can be driven with no external amplifier. the stac9766/67 may be used as a secondary codec, with the stac9700/21/44/56/ 08/84 as the primary, in a multiple codec configuration conforming to the ac'97 rev. 2.2 specification. this configuration can provide true six-channel, ac-3 playback required for dvd applications. the stac9766/67 communicates via the five-wire ac-link to any digital component of ac'97 providing flexibility in the audio system design. packaged in an ac'97 compliant 48-pin tqfp, the stac9766/67 can be placed on the motherboard, daughter boards, pci, amr, cnr, or acr cards. the stac9766/67 block diagram is illustrated in figure 1. it provides variable sam- ple rate digital-to-analog (da) and analog-to-digital (ad) conversion, mixing, and analog processing. supported audio sample rates include 48 khz, 44.1 khz, 32 khz, 22.05 khz, 16 khz, 11.025 khz, and 8 khz; additional rates are supported in the stac9766/67 soft audio drivers. the digital interface communicates with the ac'97 controller via the five-wire ac-link and contains the 64-word by 16-bit regis-
2-9766-d1-6.0-0802 7 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 ters. the two dacs convert the digital stereo pcm-out content to audio. the mixer block combines the pcm_out with any analog sources, to drive the line_out and hp_out outputs. the mono_out delivers either mic only, or a mono mix of sources from the mixer. the stereo variable sample rate adc ? s provide record capability for any mix of mono or stereo sources, and deliver a digital stereo pcm-in signal back to the ac-link. the microphone input and mono input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. all adc's operate at 18-bit resolution and dac ? s at 20-bit resolution. for a digital ready record path, the microphone is connected to the left channel adc while the mono output of the stereo mixer is connected to right channel adc. make sure the microphone input is not connected to the stereo mixer when in this mode. the stac9766/67 supports general purpose input/output (gpio), as well as spdif output. these digital i/o options provide for a number of advance architec- tural implementations, with volume controls and digital mixing capabilities built directly into the codec. the stac9766/67 is designed primarily to support stereo (2-speaker) audio. true ac-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option available in the stac9766/67 to support multiple codecs in an ac'97 architecture. additionally, the stac9766/67 provides for a stereo enhancement feature, sigmatel surround 3d (ss3d). ss3d provides the listener with several options for improved speaker separation beyond the normal 2/ 4-speaker arrangements. together with the logic component (controller or advanced core logic chip-set) of ac'97, stac9766/67 can be soundblaster ? and windows sound system ? com- patible with sigmatel ? s wdm driver for win 98/2k/me/xp. soundblaster is a regis- tered trademark of creative labs. windows is a registered trademark of microsoft corporation. 2.3. ordering information part number package temp range supply range STAC9766T 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 5.0v stac9767t 48-pin tqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 3.3v
8 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 2.4. stac9766/67 block diagram 2.5. key specifications analog line_out snr: 103 db digital dac snr: 95 db digital adc snr: 85 db full-scale total harmonic distortion: 0.002% crosstalk between input channels: -70 db spurious tone rejection: 100 db 2.6. related materials product brief reference designs for mb, amr, cnr, and acr applications audio precision performance plots 2.7. additional support additional product and company information can be obtained by going to the sigmatel website at: www.sigmatel.com figure 1. stac9766/67 block diagram hp_out ac-link digital interface registers 64x16 bits sync bit_clk sdata_out sdata_in reset# power management dac dac adc adc pcm out dacs pcm in adcs 4 stereo sources 2 mono sources mono_out mic boost 0,20 or 30 db mic1 stereo mono mixer analog mixing and gain control m u x mic2 line_out multi-codec cid0 cid1 spdif variable sample rate 20-bit dacs and 18-bit adcs
2-9766-d1-6.0-0802 9 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3. characteristics/specifications 3.1. electrical specifications 3.1.1. absolute maximum ratings: voltage on any pin relative to ground vss - 0.3v to vdd + 0.3v operating temperature 0 o c to 70 o c storage temperature -55 o c to +125 o c soldering temperature 220 o c for 10 seconds output current per pin 4 ma except vrefout = 5ma maximum supply voltage 5.5 volts = vdd 3.1.2. recommended operating conditions 3.1.3. power consumption parameter min typ max unit power supplies* + 3.3v digital 3.135 3.3 3.465 v + 5v analog 4.75 5 5.25 v + 3.3v analog 3.135 3.3 3.465 v ambient temperature 0 - 70 o c table 1. recommended operating conditions. parameter min typ max unit digital supply current + 3.3v digital - 35 - ma analog supply current + 5v analog - 80 - ma + 3.3v analog - 70 - ma power down status pr0 supply current - tbd - ma pr1 supply current - tbd - ma pr2 supply current - tbd - ma pr3 supply current - tbd - ma pr4 supply current - tbd - ma pr5 supply current - tbd - ma pr6 supply current - tbd - ma table 2. power consumption
10 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3.1.4. ac-link static digital specifications (tambient = 25 o c, dvdd = 3.3v 5%, avss=dvss=0v; 50pf external load) 3.1.5. stac9766 analog performance characteristics (t ambient = 25 o c, avdd = 5.0v 5%, dvdd = 3.3v 5%, avss=dvss=0v; 1 khz input sine wave; sample frequency = 48 khz; 0 db = 1 vrms, 10k ?// 50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) parameter symbol min typ max unit input voltage range vin -0.30 - dvdd + 0.30 v low level input range vil - - 0.35xdvdd v high level input voltage vih 0.65xdvdd - - v high level output voltage voh 0.90xdvdd - - v low level output voltage vol - - 0.1xdvdd v input leakage current (ac-link inputs) - -10 - 10 ua output leakage current (hi-z ? d ac-link outputs) - -10 - 10 ua output buffer drive current - - 4 - ma table 3. ac-link static specifications parameter min typ max unit full scale input voltage: all analog inputs except mic - 1.0 - vrms mic inputs (note 1) - 0.03 - vrms full scale output: line output - 1.0 - vrms pcm (dac) to line_out 1.0 vrms mono_out - 1.0 - vrms headphone_out (32 ? load) - 50 - mwpk analog s/n: (note 2) cd to line_out - 103 - db other to line_out - 103 - db d/a to line_out - 95 - db line_in to a/d with high pass filter enabled - 85 - db analog frequency response (note 3) 20 - 20,000 hz total harmonic distortion: (note 4) cd to line_out - 95 - db other to line_out - 95 - db d/a to line_out (full scale) - 84 -db line_in to a/d with high pass filter enabled 84 - - db headphone_out 74 80 - db a/d & d/a digital filter pass band (note 5) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz table 4. stac9766 analog performance characteristics
2-9766-d1-6.0-0802 11 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 note: 1. with +30 db boost on, 1.0vrms with boost off 2. ratio of full scale signal to idle channel noise output is measured ? a weighted ? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 3. 1db limits for line output & 0 db gain 4. 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. for all inputs except pc beep. 3.1.6. stac9767 analog performance characteristics (t ambient = 25 o c, avdd = dvdd = 3.3v 5%, avss=dvss=0v; 1 khz input sine wave; sample frequency = 48 khz; 0 db = 1 vrms, 10k ?// 50pf load, testbench characterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 6) 100 - - db dac out-of-band rejection (note 7) 55 - - db group delay (48khz sample rate) - 1 ms a n y a n a l o g i n p u t t o l i n e _ o u t c r o s s t a l k (10khz signal frequency) 70 - - db a n y a n a l o g i n p u t t o l i n e _ o u t c r o s s t a l k (1khz signal frequency) - 100 - db spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance (note 8) - 50 - k ? input capacitance - 15 - pf vrefout - 0.5 x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db parameter min typ max unit full scale input voltage: all analog inputs except mic - 1.0 - vrms mic inputs (note 1) - 0.03 - vrms full scale output: line output - 0.5 - vrms pcm (dac) to line_out 0.5 vrms mono_out - 0.5 - vrms headphone_out (32 ? load) - 12.5 - mwpk analog s/n: (note 2) cd to line_out - 97 - db other to line_out - 97 - db d/a to line_out - 95 - db table 5. stac9767 analog performance characteristics parameter min typ max unit table 4. stac9766 analog performance characteristics (continued)
12 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 note: 1. with +30 db boost on, 1.0vrms with boost off 2. ratio of full scale signal to idle channel noise output is measured ? a weighted ? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio).0 db gain, 20 khz bw, 48 khz sample frequency 1 db limits 3. 1db limits for line output & 0 db gain 4. 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. for all inputs except pc beep. line_in to a/d with high pass filter enabled - 85 - db analog frequency response (note 3) 20 - 20,000 hz total harmonic distortion: (note 4) cd to line_out - 95 - db other to line_out - 95 - db d/a to line_out (full scale) - 84 -db line_in to a/d with high pass filter enabled - 84 - db headphone_out 74 80 - db a/d & d/a digital filter pass band (note 5) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 6) 100 - - db dac out-of-band rejection (note 7) 55 - - db group delay (48khz sample rate) - - 1 ms any analog input to line_out crosstalk (10khz signal frequency) 70 - - db any analog input to line_out crosstalk (1khz signal frequency) -100 -db spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance (note 8) - 50 - k ? input capacitance - 15 - pf vrefout - 0.5 x avdd - v interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/ o c parameter min typ max unit table 5. stac9767 analog performance characteristics (continued)
2-9766-d1-6.0-0802 13 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3.2. ac timing characteristics (t ambient = 25 c, avdd = 3.3v or 5v 5%, dvdd = 3.3v 5%, avss=dvss+0v; 50pf external load) 3.2.1. cold reset note: bit_clk and sdatain are in a high impedance state during reset. 3.2.2. warm reset parameter symbol min typ max units reset# active low pulse width tres_low 1.0 - - us reset# inactive to bit_clk startup delay trst2clk 162.8 - - ns table 6. cold reset specifications parameter symbol min typ max units sync active high pulse width tsync_high 1.0 1.3 - us sync inactive to bit_clk startup delay tsync2clk 162.8 - - ns table 7. warm reset specifications figure 2. cold reset timing tres_low trst2clk reset# bit_clk sdata_in tsync_high tsync_2clk sync bit_clk figure 3. warm reset timing
14 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3.2.3. clocks the 9766/9767 supports several clock frequency inputs as described in the follow- ing table. in general, when a 24.576mhz clock xtal is not used, the xtalout pin should be tied to ground. this short to ground configures the part into an alternate clock mode and enables an on board pll. parameter symbol min typ max units bit_clk frequency - 12.288 - mhz bit_clk period tclk_period - 81.4 - ns bit_clk output jitter - 750 - ps blt_clk high pulsewidth (note 9) tclk_high 36 40.7 45 ns bit_clk low pulse width (note 9) tclk_low 36 40.7 45 ns sync frequency - 48.0 - khz sync period tsync_period - 20.8 - us sync high pulse width tsync_high - 1.3 - us sync low_pulse width tsync_low - 19.5 - us note: 9. worst case duty cycle restricted to 45/55. table 8. clocks specifications xtl_out pin config cid1 pin config cid0 pin config clock source input codec mode codec id xtal float float 24.576mhz xtal p 0 xtal or open float pulldown 12.288mhz bit clk s 1 xtal or open pulldown float 12.288mhz bit clk s 2 xtal or open pulldown pulldown 12.288mhz bit clk s 3 short to ground float float 14.31818mhz source 1 p0 short to ground float pulldown 27mhz source p 0 short to ground pulldown float 48mhz source 2 p0 short to ground pulldown pulldown 24.576mhz source p 0 table 9. clock mode configuration note: 1. in the ca1 and ca2 revisions, this clock source input is 48mhz. note: 2. in the ca1 and ca2 revisions, this clock source input is 14.3181 mhz. sync bit_clk tclk_high tclk_low tclk_period tsync_high tclk_period tsync_low figure 4. clocks timing
2-9766-d1-6.0-0802 15 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3.2.4. data setup and hold (47.5-75pf external load) 3.2.5. signal rise and fall times (75pf external load; from 10% to 90% of vdd) parameter symbol min typ max units setup to falling edge of bit_clk tsetup 10 - - ns hold from falling edge of bit_clk thold 10 - - ns note: setup and hold time parameters for sdata_in are with respect to the ac ? 97 controller. table 10. data setup and hold specifications parameter symbol min typ max units bit_clk rise time triseclk - - 6 ns bit_clk fall time tfallclk - - 6 ns sdata_in rise time trisedin - - 6 ns sdata_in fall time tfalldin - - 6 ns table 11. signal rise and fall times specifications bit_clk t hold t setup sdata_out sdata_in sync tco v ih v il v oh v ol figure 5. data setup and hold timing bit_clk sdata_in tfallclk triseclk trisedin tfalldin figure 6. signal rise and fall times timing
16 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 3.2.6. ac-link low power mode timing 3.2.7. ate test mode note: 1. all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the trailing edge of reset# causes stac9766/67 ac-link outputs to go high impedance which is suitable for ate in circuit testing. 2. once the test mode has been entered, the stac9766/67 must be issued another reset# with all ac-link signals low to return to the normal operating mode. 3. # denotes active low. parameter symbol min typ max units end of slot 2 to bit_clk, sdata_in low ts2_pdown - - 1.0 us table 12. ac-link low power mode timing specifications parameter symbol min typ max units setup to trailing edge of reset# (also applies to sync) tsetup2rst 15.0 - - ns rising edge of reset# to hi-z delay toff - - 25.0 ns table 13. ate test mode specifications bit_clk sdata_in note: bit_clk not to scale ts2_pdown don ? t care data pr4 write to 0x20 slot 2 slot 1 sdata_out sync figure 7. ac-link low power mode timing tsetup2rst hi-z toff reset# sdata_out sdata_in, bit_clk figure 8. ate test mode timing
2-9766-d1-6.0-0802 17 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 4. typical connection diagram 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f 2 ? * ferrite bead* *suggested 3.3v 5% avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 cap2 32 *optional 0.1 f 1 f* 820 pf 29 30 afilt1 afilt2 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 line_out_r 35 line_out_l 43 gpio0 44 gpio1 40 hp_comm 48 spdif 34 nc 33 nc 31 nc 0.1 f 1 f* *optional 27 vref vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 sdata_in bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter *optional stac9767 note: 1. see appendix a for specific connection requirements prior to operation. 2. see figure 24 on page 60 for split supply connections. 3. pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating. figure 9. stac9767 typical connection diagram
18 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 5. ac-link figure 10 shows the ac-link point to point serial interconnect between the stac9766/67 and its companion controller. all digital audio streams and com- mand/status information are communicated over this ac-link. see ? digital inter- face ? on page 19 for details. 5.1. clocking stac9766/67 derives its clock internally from an externally connected 24.576 mhz crystal or an oscillator through the xtal_in pin. synchronization with the ac'97 controller is achieved through the bit_clk pin at 12.288 mhz. the beginning of all audio sample packets, or ? audio frames ? , transferred over ac-link is synchronized to the rising edge of the ? sync ? signal driven by the ac'97 controller. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled by the receiving side on each immediately following falling edge of bit_clk. 5.2. reset there are 3 types of resets: 1. a ? cold ? reset where all stac9766/67 logic and registers are initialized to their default state 2. a ? warm ? reset where the contents of the stac9766/67 register set are left unaltered 3. a ? register ? reset which only initializes the stac9766/67 registers to their default states after signaling a reset to the stac9766/67 , the ac'97 controller should not attempt to play or capture audio data until it has sampled a ? codec ready ? indication via register 26h from the stac9766/67 . for proper reset operation sdata_out should be ? 0 ? during ? cold ? reset. sync digital dc ? 97 controller ac ? 97 codec bit_clk sdata_out sdata_in reset# xtal_in xtal_out figure 10. ac-link to its companion controller
2-9766-d1-6.0-0802 19 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6. digital interface 6.1. ac-link digital serial interface protocol the stac9766/67 communicates to the ac ? 97 controller via a 5-pin digital serial ac-link interface, which is a bi-directional, fixed rate, serial pcm digital stream. all digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. the ac-link handles multiple inputs, and out- put audio streams, as well as control register accesses using a time division multi- plexed (tdm) scheme. the ac ? 97 controller synchronizes all ac-link data transaction. table 14 shows the data streams available on the stac9766/67 : synchronization of all ac-link data transactions is handled by the ac ? 97 controller. the stac9766/67 drives the serial bit clock onto ac-link. the ac ? 97 controller then qualifies with a synchronization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to sup- port 12, 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, stac9766/67 for outgoing data and ac ? 97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a ? 1 ? in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is ? tagged ? invalid, it is the responsibility of the source of the data, (stac9766/67 for the input stream, ac'97 controller for the output stream), to stuff all bit positions with 0 ? s during that slot ? s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ? tag phase ? . the remainder of the audio frame where sync is low is defined as the ? data phase ? . additionally, for power savings, all clock, sync, and data signals may be halted by the controller. pcm playback 2 output slots 2 channel composite pcm output stream pcm record data 2 input slots 2 channel composite pcm input stream control 2 output slots control register write port status 2 input slots control register read port table 14. stac9766/67 available data streams outgoing streams incoming streams sync tag phase data phase pcm left cmd adr na pcm lsurr pcm lfe pcm ralt tag cmd data pcm rt pcm ctr pcm rsurr pcm lalt rsvd pcm left status adr na rsvd rsvd rsvd tag status data pcm rt na rsvd rsvd rsvd figure 11. ac?97 standard bi-directional audio frame
20 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.1. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the stac9766/67 dac inputs, and control registers. each audio output frame supports up to twelve 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the ? valid frame ? bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the stac9766/67 indicate which of the corresponding 12 times slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48khz audio frame rate. the following dia- gram illustrates the time slot based ac-link protocol. a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the stac9766/67 samples the assertion of sync. this following edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac'97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit posi- tion is presented to ac-link on a rising edge of bit_clk, and subsequently sam- pled by the stac9766/67 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_out ? s composite stream is msb justified (msb first) with all non-valid slots ? bit positions stuffed with 0 ? s by the ac'97 controller. when mono audio sample streams are sent from the ac'97 controller, it is neces- sary that both left and right sample stream time slots be filled with the same data. sync bit_clk sdata_out slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) cid1 cid0 valid "0" 19 19 "0" frame 19 "0" "0" figure 12. ac-link audio output frame sync bit_clk sdata_out slot1 slot2 end of previous audio frame valid frame sync asserted first sdata_out bit of frame figure 13. start of an audio output frame
2-9766-d1-6.0-0802 21 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.1.1. slot 1: command address port the command port is used to control features, and monitor status (see audio input frame slots 1 and 2) of the stac9766/67 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). the control interface architecture supports up to sixty-four 16-bit read/write regis- ters, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. odd accesses are considered invalid and return 0 0 0 0. audio output frame slot 1 communicates control register address, and write/read command information to the stac9766/67. the first bit (msb) sampled by stac9766/67 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0 ? s by the ac ? 97 controller. 6.1.1.2. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by slot 1, bit 19). if the current command port operation is a read then the entire slot time must be stuffed with 0 ? s by the ac ? 97 controller. 6.1.1.3. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical ? games compatible ? pc this slot is composed of standard pcm (.wav) out- put samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is trans- ferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 6.1.1.4. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical ? games compatible ? pc this slot is composed of standard pcm (.wav) out- put samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is trans- ferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. bit description comments 19 read/write command 1= read, 0=write 18:12 control register index sixty-four 16-bit locations, addressed on even byte boundaries 11:0 reserved stuffed with 0 ? s table 15. command address port bit assignments bit description comments 19:4 control register write data stuffed with 0 ? s if current operation is a read 3:0 reserved stuffed with 0 ? s table 16. command data port bit assignments
22 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.1.5. slot 5: reserved audio output frame slot 5 is reserved for modem operation and is not used by the stac9766/67. 6.1.1.6. slot 6: pcm center channel audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the stac9766/67 is programmed to accept the pri- mary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.7. slot 7: pcm left surround channel audio output frame slot 7 is the composite digital audio left surround stream. in the default state, the stac9766/67 accepts pcm data from slots 7 and 8 for the sur- round dacs, for output to the dac_out pins. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs when slots 6 and 9 are used to drive the surround dacs. please refer to the register program- ming section for details on the multi-channel programming options. 6.1.1.8. slot 8: pcm right surround channel audio output frame slot 8 is the composite digital audio right surround stream. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.9. slot 9: pcm low frequency channel audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the stac9766/67 is programmed to accept the primary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel programming options. 6.1.1.10. slot 10: pcm alternate left audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel applications. please refer to the register programming section for details on the multi channel programming options. 6.1.1.11. slot 11: pcm alternate right audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel applications. please refer to the register programming section for details on the multi channel programming options. 6.1.1.12. slot 12: reserved audio output frame slot 12 is reserved for modem operations and is not used by the stac9766/67.
2-9766-d1-6.0-0802 23 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.2. ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac ? 97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infra- structure. within slot 0 the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the stac9766/67 is in the ? codec ready ? state or not. if the ? codec ready ? bit is a 0, this indicates that stac9766/67 is not ready for normal operation. this condition is normal following the de-assertion of power on reset, for example, while stac9766/67 ? s voltage references settle. when the ac-link ? codec ready ? indica- tor bit is a 1, it indicates that the ac-link and stac9766/67 control/status registers are in a fully operational state. the ac'97 controller must further probe the power- down control status register (refer to mixer register section) to determine exactly which subsections, if any, are ready. prior to any attempts at putting stac9766/67 into operation the ac'97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indi- cation that stac9766/67 has become ? codec ready ? . once the stac9766/67 is sampled ? codec ready ? , the next 12 bit positions sampled by the ac'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. the following diagram illustrates the time slot based ac-link protocol. a new audio input frame begins with a low to high transition of sync. sync is syn- chronous to the rising edge of bit_clk. immediately following the falling edge of bit_clk, the stac9766/67 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the stac9766/67 transitions sdata_in into the first bit position of slot 0 ( ? codec ready ? bit). each new bit position is presented to ac-link on a rising edge of bit_clk and subsequently sampled by the ac'97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_in's composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by stac9766/ 67. sdata_in data is sampled on the falling edges of bit_clk. sync bit_clk sdata_in slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) valid "0" 19 19 "0" frame 19 "0" "0" "0" "0" figure 14. stac9766/67 audio input frame
24 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.2.1. slot 1: status address port the status port is used to monitor status for stac9766/67 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1 ? s stream echoes the control register index, for historical ref- erence, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ? valid ? by stac9766/67 during slot 0) the first bit (msb) generated by stac9766/67 is always stuffed with a 0. the fol- lowing 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by stac9766/67. 6.1.2.2. slot 2: status data port the status data port delivers 16-bit control register read data. if slot 2 is tagged ? invalid ? by stac9766/67 , then the entire slot will be stuffed with 0's. 6.1.2.3. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. bit description comments 19 reserved stuffed with 0 ? s 18:12 control register index echo of register index for which data is being returned 11:3 slot request see sections below 2:0 reserved stuffed with 0 ? s table 17. status address port bit assignments bit description comments 19:4 control register read data stuffed with 0's if tagged ? invalid ? 3:0 reserved stuffed with 0's table 18. status data port bit assignments sync bit_clk sdata_in slot1 slot2 end of previous audio frame codec ready sync asserted first sdata_out bit of frame figure 15. start of an audio input frame
2-9766-d1-6.0-0802 25 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.2.4. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of stac9766/67 input mux, post-adc. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. 6.1.2.5. slot 5: reserved audio input frame slot 5 is reserved for modem operation and is not used by the stac9766/67. this slot is always stuffed with 0 ? s. 6.1.2.6. slot 6: pcm left record channel audio input frame slot 6 is the left channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings. 6.1.2.7. slot 7: pcm left record channel audio input frame slot 7 is the left channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings. 6.1.2.8. slot 8: pcm right record channel audio input frame slot 8 is the right channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings. 6.1.2.9. slot 9: pcm right record channel audio input frame slot 9 is the right channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings.
26 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.1.2.10. slot 10: pcm left record channel audio input frame slot 10 is the left channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings. 6.1.2.11. slot 11: pcm right record channel audio input frame slot 11 is the right channel output of stac9766/67 input mux, post-adc. stac9766/67 adcs are implemented to support 18-bit resolution. stac9766/67 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 ? s to fill out its 20-bit time slot. see section 7.5.18; page 44 for slot configurations and register settings. 6.1.2.12. slot 12: reserved audio input frame slot 12 is reserved for modem operation and is not used by the stac9766/67. this slot is always stuffed with 0 ? s. 6.2. ac-link low power mode the stac9766/67 ac-link can be placed in the low power mode by programming register 26h to the appropriate value. both bit_clk and sdata_in will be brought to, and held at a logic low voltage level. the ac ? 97 controller can wake up the stac9766/67 by providing the appropriate reset signals. bit_clk and sdata_in are transitioned low immediately (within the maximum specified time) following the decode of the write to the powerdown register (26h) with pr4. when the ac ? 97 controller driver is at the point where it is ready to pro- gram the ac-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). the ac ? 97 controller should also drive sync, and sdata_out low after program- ming the stac9766/67 to this low power mode. sync bit_clk sdata_out note: bit_clk not to scale sdata_in tag write to 0x20 slot 2 per frame data pr4 tag slot 2 per frame figure 16. stac9766/67 powerdown timing
2-9766-d1-6.0-0802 27 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 6.3. waking up the ac-link once the stac9766/67 has halted bit_clk, there are only two ways to ? wake up ? the ac-link. both methods must be activated by the ac'97 controller. the ac-link protocol provides for a ? cold ac'97 reset ? , and a ? warm ac'97 reset ? . the current power down state would ultimately dictate which form of reset is appropriate. unless a ? cold ? or ? register ? reset (a write to the reset register) is performed, wherein the ac'97 registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15). cold reset - a cold reset is achieved by asserting reset# for the minimum speci- fied time, and then bringing reset# back high. the reset occurs on the rising edge when reset# is deasserted. by asserting and deasserting reset#, bit_clk and sdata_in will be activated, or re-activated as the case may be, and all stac9766/67 control registers will be initialized to their default power on reset values. note: reset# is an asynchronous input. (# denotes active low) warm reset - a warm reset will re-activate the ac-link without altering the current stac9766/67 register values. a warm reset is signaled by driving sync high for a minimum of 1us in the absence of bit_clk. note: within normal audio frames, sync is a synchronous input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the stac9766/67.
28 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7. stac9766/67 mixer the stac9766/67 includes analog and digital mixers for maximum flexibility. the analog mixer is designed to the ac ? 97 specification to manage the playback and record of all digital and analog audio sources in the pc environment. the analog mixer also includes several extensions of the ac ? 97 specification to support ? all ana- log record ? capability as well as ? pop bypass ? mode for all digital playback. the analog sources include: system audio : digital pcm input and output for business, games and multime- dia cd/dvd : analog cd/dvd-rom audio with internal connections to codec mixer mono microphone : choice of desktop mic, with programmable boost and gain speakerphone : use of system mic and speakers for telephone, dsvd, and video conferencing video : tv tuner or video capture card with internal connections to codec mixer aux/synth : analog fm or wavetable synthesizer, or other internal source the digital mixer includes inputs for the pcm dac and the recorded adc output. source function connection pc_beep pc beep pass through to line_out from pc_beep output phone mono input from telephony subsystem mic1 desktop microphone from mic jack mic2 second microphone from second mic jack line_in external audio source from line-in jack cd audio from cd-rom cable from cd-rom video audio from tv tuner or video camera cable from tv or vidcap card aux upgrade synth or other external source internal connector pcm out digital audio output from ac ? 97 controller ac-link destination function connection hp_out stereo mix of all sources to headphone out jack line_out stereo mix of all sources to output jack mono_out mic or mono analog mixer output to telephony subsystem pcm in digital data from the codec to the ac ? 97 controller ac-link spdif spdif digital audio output to spdif output connector
2-9766-d1-6.0-0802 29 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 20 or 30 db allanalog vs allrecord 6eh:d12 -6db mux adc 04h mono volume master volume 3d line_out 3d hp_out 02h 06h mux 1ch 20h:d15 analog audio sources slot select slot select mux pcm to spdif spdif pcmout 2ah:d5-d4 28h: d5-d4 pcmin ganged3dcontrol 20h:d13 22h:d2-d3 1ah -6db monoanalog stereoanalog digital key 20h:d9 adcrecord 6e:d2 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux dac 3d record volume 6ah:d1 18h headphone volume mono_out 0eh:d6 slot select figure 17. stac9766 2-channel mixer functional diagram 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 allanalog vs allrecord 6eh:d12 -6db mux 04h mono volume master volume 02h 06h mux 1ch 20h:d15 analog audio sources 1ah -6db monoanalog stereoanalog digital key 20h:d9 adcrecord 0eh:d6 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux 3d record volume +6db -6db -6db -6db -6db -6db -6db 18h headphone volume -6db 20 or 30 db 6e:d2 slot select slot select mux pcmout 2ah:d5-d4 dac adc 3d line_out 3d hp_out pcmin ganged3dcontrol 20h:d13 22h:d2-d3 mono_out slot select 28h: d5-d4 pcm to spdif spdif 6ah:d1 figure 18. stac9767 2-channel mixer functional diagram
30 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.1. analog mixer input the mixer provides recording and playback of any audio sources or output mix of all sources. the stac9766/67 supports the following input sources: any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix) note: all unused inputs should be tied together and have a capacitor (0.1 f suggested) to ground. 7.2. analog mixer output the mixer generates three distinct outputs: a stereo mix of all sources for output to the line_out and hp_out a stereo mix of all analog sources for recording mic only or mono mix of all sources for mono_out note:mono output of stereo mix is attenuated by -6 db. 7.3. spdif digital mux the stac9766/67 incorporates a digital output that supports spdif formats. a mul- tiplexer determines which of two digital input streams are used for the digital output conversion process. these two streams include the pcm out data from the audio controller and the adc recorded output. the normal analog line_out signal can be converted to the spdif formats by using the internal adc to record the ? mix ? output, which is the combination of all analog and all digital sources. in the case of digital controllers with support for 4 or more channels, the spdif output mode can be used to support compressed 6-channel output streams for delivery to home the- ater systems. these can be routed on alternate ac-link slots to the spdif output, while the standard 2-channel output is delivered as selected by bits d5 and d4 in register 6e. if the digital controller supports 6 channels, a spdif output with 4 ana- log channels can also be configured. for more information for spdif please see 7.5.11.2; page 40. pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating. 7.4. pc beep implementation pc beep is active on power up and defaults to an un-muted state. the pc-beep input is routed directly to the mono_out, line_out and hp_out pins of the codec. because the pc_beep input drive is often a full scale digital signal, some resistive attenuation of the pc_beep input is recommended to keep the beep tone within reasonable volume levels. the user should mute this input before using any other mixer input because the pc beep input can contribute noise to the lineout dur- ing normal operation.
2-9766-d1-6.0-0802 31 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5. programming registers address name default location 00h reset 6990h 7.5.1; page 32 02h master volume 8000h 7.5.2.1; page 32 04h hp_out mixer volume 8000h 7.5.2.2; page 32 and 35 06h master volume mono 8000h 7.5.2.3; page 33 0ah pc beep mixer volume 0000h 7.5.3; page 33 0ch phone mixer volume 8008h 7.5.4.1; page 34 0eh mic mixer volume 8008h 7.5.4.2; page 34 10h line in mixer volume 8808h 7.5.4.3; page 34 12h cd mixer volume 8808h 7.5.4.4; page 34 14h video mixer volume 8808h 7.5.4.5; page 35 16h aux mixer volume 8808h 7.5.4.6; page 35 18h pcm out mixer volume 8808h 7.5.4.7; page 35 1ah record select 0000h 7.5.5; page 36 1ch record gain 8000h 7.5.6; page 36 20h general purpose 0000h 7.5.7; page 37 22h 3d control 0000h 7.5.8; page 37 26h powerdown ctrl/stat 000fh 7.5.9; page 38 28h extended audio id 0205h 7.5.10; page 39 2ah extended audio control/status 0400h 7.5.11; page 40 2ch pcm dac rate bb80h 7.5.13; page 42 32h pcm lr adc rate bb80h 7.5.14; page 42 3ah spdif control 2a00h 7.5.15; page 42 6ah digital audio control 0000h 7.5.15; page 42 6ch revision code 0000h 7.5.17; page 44 6eh analog special 0000h 7.5.18; page 44 70h 72h enable 0000h 7.5.18.5; page 45 72h analog current adjust 0000h 7.5.18.6; page 45 74h gpio current access 0000h 7.5.19; page 46 76h 78h enable 0000h 7.5.20.1; page 47 78h clock access 0000h 7.5.20.2; page 47 7ch vendor id1 8384h 7.5.21.1; page 48 7eh vendor id2 7666h 7.5.21.2; page 48 table 19. programming registers
32 2-9766-d1-6.0-0802 stac9766/67 two-channel ac?97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.1. reset (00h) default: 6990h writing any value to this register performs a register reset, which causes all regis- ters to revert to their default values. reading this register returns the id code of the part. 7.5.2. play master volume registers (index 02h, 04h, and 06h) these registers manage the output signal volumes. register 02h controls the stereo line_out master volume (both right and left channels), register 04h controls the headphone out master volume, and register 06h controls the mono volume out- put. each step corresponds to 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 through ml0 is for left channel level, mr5 through mr0 is for the right channel and mm5 through mm0 is for the mono out channel. when bits d5 and d13 are set in any of these registers it automatically writes all 1 ? s to the next lower 5-bits. the default value is 8000h for registers 02h, 04h, and 06h, which corresponds to 0 db attenuation with mute on. 7.5.2.1. master volume (02h) default: 8000h note: if optional bits d13, d5 of register 02h are set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 1fh as a value for this attenuation/gain block. 7.5.2.2. headphone out volume (04h) default: 8000h if optional bits d13, d5 of register 04h are set to 1, then the corresponding attenua- tion is set to 46db and the register reads will produce 1fh as a value for this attenu- ation/gain block. d15 d14 d13 d12 d11 d10 d9 d8 rsrvd4 se4 se3 se2 se1 se0 id9 id8 d7 d6 d5 d4 d3 d2 d1 d0 id7 id6 id5 id4 id3 id2 id1 id0 mute mx 5 ? mx0 function range 0 00 0000 0db attenuation req. 0 01 1111 46.5 attenuation req. 1 xx xxxx db attenuation req. table 20. play master volume register d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 reserved mr5 mr4 mr3 mr2 mr1 mr0 d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hpr5 hpr4 hpr3 hpr2 hpr1 hpr0
2-9766-d1-6.0-0802 33 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.2.3. master volume mono (06h) default: 8000h note: if optional bits d5 of register 06h is set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 1fh as a value for this attenuation/gain block. 7.5.3. pc beep mixer volume (index 0ah) default: 0000h note: pc_beep default to 0000h, mute off. this register controls the level for the pc beep input. each step corresponds to approximately 3 db of attenuation. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel is set at - db. pc_beep supports motherboard implementations. the intention of routing pc_beep through the stac9766/67 mixer is to eliminate the requirement for an onboard speaker by guar- anteeing a connection to speakers connected via the output jack. in order for this to be viable the pc_beep signal needs to reach the output jack at all times. note: the pc_beep is routed to the mono outputs when the stac9766/67 is in a reset state. this is so that power on self test (post) codes can be heard by the user in case of a hardware problem with the pc. for further pc_beep implementation details please refer to the ac ? 97 technical faq sheet. the default value is 0000h, which corresponds to 0 db attenuation with mute off. d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved pv3 pv2 pv1 pv0 rsrvd mute pv3 ? pv0 function 0 0000 0 db attenuation 0 1111 45 db attenuation 1xxxx db attenuation table 21. pc_beep register
34 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.4. analog mixer input gain registers (index 0ch - 18h) these registers control the gain/attenuation for each of the analog inputs. each step corresponds to approximately 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. the default value for stereo registers is 8808h, corresponding to 0 db gain with mute on. 7.5.4.1. phone mixer volume (0ch) default: 8008h 7.5.4.2. mic mixer volume (0eh) default: 8008h register 0eh (mic volume register) bit d6 is the mic boost enable. to select between 20db or 30db mic boost, see register 6eh, d2 in section 7.5.18; page 44. 7.5.4.3. line in mixer volume (10h) default: 8808h 7.5.4.4. cd mixer volume (12h) default: 8808h mute gx4 ? gx0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 -34.5 db gain table 22. analog mixer input gain register d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 rsrvd boost_en rsrvd gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0
2-9766-d1-6.0-0802 35 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.4.5. video mixer volume (14h) default: 8808h 7.5.4.6. aux mixer volume (16h) default: 8808h 7.5.4.7. pcm out mixer volume (18h) default: 8808h d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0
36 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.5. record select (1ah) default: 0000h (corresponding to mic in) used to select the record source independently for right and left. 7.5.6. record gain (1ch) default: 8000h (corresponding to 0 db gain with mute on) the 1ch register adjusts the stereo input record gain. each step corresponds to 1.5 db. 22.5 db corresponds to 0f0fh. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. d15 d14 d13 d12 d11 d10 d9 d8 reserved sl2 sl1 sl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved sr2 sr1 sr0 bit(s) reset value name description 15:11 0 reserved bits not used, should read back 0 10:8 0 sl2:sl0 left channel input select 000 = mic 001 = cd in (left) 010 = video in (left) 011 = aux in (left) 100 = line in (left) 101 = stereo mix (left) 110 = mono mix 111 = phone 7:3 0 reserved bits not used, should read back 0 2:0 0 sr2:sr0 right channel input select 000 = mic 001 = cd in (right) 010 = video in (right) 011 = aux in (right) 100 = line in (right) 101 = stereo mix (right) 110 = mono mix 111 = phone table 23. record select control registers d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr3 gr2 gr1 gr0 mute gx3 ? gx0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1xxxx- gain table 24. record gain registers
2-9766-d1-6.0-0802 37 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.7. general purpose (20h) default: 0000h this register is used to control some miscellaneous functions. below is a summary of each bit and its function. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. 7.5.8. 3d control (22h) default: 0000h this register is used to control the 3d stereo enhancement function, sigmatel sur- round 3d (ss3d), built into the ac ? 97 component. note that register bits dp3-dp2 are used to control the separation ratios in the 3d control for line_out. ss3d pro- vides for a wider soundstage extending beyond the normal 2-speaker arrangement. note that the 3d bit in the general purpose register (20h) must be set to 1 to enable ss3d functionality and for the bits in 22h to take effect. the three separation ratios are implemented as shown in table 26. the separation ratio defines a series of equations that determine the amount of depth difference (high, medium, and low) perceived during two-channel playback. the ratios pro- vide for options to narrow or widen the soundstage. d15 d14 d13 d12 d11 d10 d9 d8 pop byp rsrvd 3d reserved mix ms d7 d6 d5 d4 d3 d2 d1 d0 lpbk reserved bit function 3d 3d stereo enhancement on/off 1 = on mix mono output select 0 = mix, 1= mic ms mic select 0 = mic1, 1 = mic2 pop byp dac bypasses mixer and connects directly to line out lpbk adc/dac loopback mode table 25. general purpose register d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dp3 dp2 reserved dp3, dp2 line_out separation ratio 0 0 0 (off) 0 1 3 (low) 1 0 4.5 (med) 1 1 6 (high) table 26. 3d control registers
38 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.9. powerdown ctrl/stat (26h) default: 000fh this read/write register is used to program powerdown states and monitor sub- system readiness. the eapd external control is also supported through this regis- ter. 7.5.9.1. ready status the lower half of this register is read only status, a ? 1 ? indicating that the subsection is ? ready ? . ready is defined as the subsection's ability to perform in its nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. when the ac-link ? codec ready ? indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac'97 control and status registers are in a fully oper- ational state. the ac'97 controller must further probe this powerdown control/sta- tus register to determine exactly which subsections, if any are ready. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. 7.5.9.2. powerdown controls the stac9766/67 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). see the section ? low power modes ? for more information. 7.5.9.3. external amplifier power down control the eapd bit 15 of the powerdown control/status register (index 26h) directly controls the output of the eapd output, pin 45, and produces a logical ? 1 ? when this bit is set to logic high. this function is used to control an external audio amplifier power down. eapd = 0 places approximately 0v on the output pin, enabling an external audio amplifier. eapd = 1 places approximately dvdd on the output pin, disabling the external audio amplifier. audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibil- ity. d15 d14 d13 d12 d11 d10 d9 d8 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 d7 d6 d5 d4 d3 d2 d1 d0 reserved ref anl dac adc bit function eapd external amplifier power down ref vref ? s up to nominal level anl analog mixers, etc. ready dac dac section ready to playback data adc adc section ready to playback data table 27. powerdown status registers
2-9766-d1-6.0-0802 39 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.10. extended audio id (28h) default: 0605h the extended audio id register is a read only register, except for bits d5:d4. id1 and id0 echo the configuration of the codec as defined by the programming of pins 45 and 46 externally. ? 00 ? returned defines the codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. sdac=0 tells the controller that the stac9766/67 is a two-channel codec as defined by the intel spec. the amap bit, d9, will return a 1 indicating that the codec supports the optional ? ac ? 97 2.2 compliant ac-link slot to audio dac mappings ? . the default condition assumes that 0, 0 are loaded in the dsa0 and dsa1 bits of the extended audio id (index 28h). with 0s in the dsax bits, the codec slot assign- ments are as per the ac ? 97 specification recommendations. if the dsax bits do not contain 0s, the slot assignments are as per the table in the section describing the extended audio id (index 28h). the vra bit, d0, will return a 1 indicating that the codec supports the optional variable sample rate conversion as defined by the ac ? 97 specification. 1. external cid pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46). these bits are zero if xtal_out is grounded with an alternate external clock source in primary mode d15 d14 d13 d12 d11 d10 d9 d8 id1 id0 reserved rev1 rev0 amap ldac d7 d6 d5 d4 d3 d2 d1 d0 sdac cdac dsa1 dsa0 vrm spdif dra vra bit name access reset value function 15:14 id [1,0] read only variable 0,0=xtal_out grounded (note 1) cid1#,cid0#=xtal_out crystal or floating 13:12 reserved read only 00 reserved 11:10 rev[1:0] read only 01 indicates codec is ac ? 97 rev 2.2 compliant 9 amap read only 1 multi-channel slot support (always = 1) 8 ldac read only 0 low frequency effect, not supported (always=0) 7 sdac read only 0 surround dac, not supported (always = 0) 6 cdac read only 0 center channel, not supported (always = 0) 5:4 dsa [1,0] read/write 00 dac slot assignment if cid[1:0]=00 then dsa[1:0] resets to 00 if cid[1:0]=01 then dsa[1:0] resets to 01 if cid[1:0]=10 then dsa[1:0] resets to 01 if cid[1:0]=11 then dsa[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 3 vrm read only 0 variable sample rate mic, not supported (always = 0) 2 spdif read only 1 0=spdif pulled high on reset, spdif disabled 1=default, spdif enabled (note 2) 1 dra read only 0 double rate audio,not supported (always = 0) 0 vra read only 1 variable sample rates supported (always = 1) table 28. extended audio id
40 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 only. secondary mode can either be through bit clk driven or 24mhz clock driver with xtal_out floating/shorted. 2. if pin 48 is held high at powerup, this bit will be held to zero, to indicate the spdif is not available. pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating. 7.5.11. extended audio control/status (2ah) default: 0400h 7.5.11.1. variable rate sampling enable the extended audio status control register also contains one active bit to enable or disable the variable sampling rate capabilities of the dacs and adcs. if the vra, bit d0, is 1 the variable sample rate control registers (2ch and 32h) are active, and ? on-demand ? slot data required transfers are allowed. if the vra bit is 0, the dacs and adcs will operate at the default 48 khz data rate. the stac9766/67 supports ? on-demand ? slot request flags. these flags are passed from the codec to the ac ? 97 controller in every audio input frame. each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next pcm sample for the corresponding slot in the audio frame that immediately follows. the vra enable bit must be set to 1 to enable ? on-demand ? data transfers. if the vra enable bit is not set, the codec will default to 48 khz transfers and every audio frame will include an active slot request flag and data is transferred every frame. for variable sample rate output, the codec examines its sample rate control regis- ters, the state of the fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. thus, even in variable sample rate mode, the codec is always the master: for sdata_in (codec to controller), the codec sets the tag bit; for sdata_out (controller to codec), the codec sets the slotreq bit and then checks for the tag bit in the next frame. whenever vra is set to 0 the pcm rate registers (2ch and 32h) are overwritten with bb80h (48 khz). 7.5.11.2. spdif the spdif bit in the extended audio status control register is used to enable and disable the spdif functionality within the stac9766/67. if the spdif is set to a 1, then the function is enabled and when set to a 0 it is disabled. d15 d14 d13 d12 d11 d10 d9 d8 reserved spcv reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved spsa1 spsa0 rsrvd spdif rsrvd vra enable
2-9766-d1-6.0-0802 41 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.11.3. spcv (spdif configuration valid) the spcv bit is read only and indicates whether or not the spdif system is set up correctly. when spcv is a 0, it indicates the system configuration is invalid and valid if it is a 1. 7.5.11.4. spsa1, spsa0 (spdif slot assignment) spsa1 and spsa0 combine to provide the slot assignments for the spdif data. the following details the slot assignment relationship between spsa1 and spsa0. the stac9766/67 are amap compliant with the following table. 7.5.12. pcm dac rate registers (2ch and 32h) the internal sample rate for the dacs and adcs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in hz. in vra mode (register 2ah bit d0 = 1), if the value written to these registers is supported that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. per pc 99 / pc 2001 specification, independent sample rates are sup- ported for record and playback. whenever vra is set to 0 the pcm rate registers (2ch and 32h) will readback with bb80h (48 khz). spsa[1,0] slot assignment comments 00 3 & 4 spdif source data slot assignment 01 7 & 8 2-ch codec primary default 10 6 & 9 4-ch codec primary default 11 10 & 11 6-ch codec primary default table 29. slot assignment relationship between spsa1 and spsa0 codec id function spsa = 00 spsa = 01 spsa = 10 spsa = 11 00 2-ch primary w/spdif 3 & 4 7 & 8* 6 & 9 10 & 11 01 2-ch dock codec w/spdif 3 & 4 7 & 8 6 & 9* 10 & 11 10 +2-ch surr w/ spdif 3 & 4 7 & 8 6 & 9* 10 & 11 11 +2-ch cntr/lfe w/ spdif 3 & 4 7 & 8 6 & 9 10 & 11* note:* is the default slot assignment table 30. stac9766/67 amap compliant sample rate sr15-sr0 value 8 khz 1f40h 11.025 khz 2b11h 16 khz 3e80h 22.05 khz 5622h 32 khz 7d00h 44.1 khz ac44h 48 khz bb80h table 31. hardware supported sample rates
42 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.13. pcm dac rate (2ch) default: bb80h 7.5.14. pcm lr adc rate (32h) default: bb80h 7.5.15. spdif control (3ah) default: 2a00h register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel status (or sub-frame in the v case). with exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit register 2 ah is ? 0 ? ). this ensures that control and status information start up correctly at the beginning of spdif transmission. the default is 2a00h which sets the spdif output sample rate at 48khz and the normal spdif expectations . d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 #v drs spsr1 spsr2 l cc6 cc5 cc4 d7 d6 d5 d4 d3 d2 d1 d0 cc3 cc2 cc1 cc0 pre copy #pcm/audio pro bit(s) reset value access name description (note 1-2) 15 0 read & write #v validity bit is set indicating each sub-frame ? s samples are invalid. if #v is 0, then it indicates that each sub-frame was transmitted and received correctly by the interface. 14 0 read only drs 1 = double rate spdif support (always = 0) 13:12 10 read & write spsr[1,0] spdif sample rate. 00 44.1 khz rate 01 reserved 10 48 khz rate (default) 11 32 khz rate 11 0 read & write l generation level is defined by the iec standard, or as appropriate. (always = 1) 10:4 0 read & write cc[6, 0] category code is defined by the iec standard or as appropriate by media. table 32. spdif control
2-9766-d1-6.0-0802 43 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 1. if pin 48 is held high at powerup, 28h d2 will be low indicating no spdif available and the register 3ah will then read back 0000h. 2. bits d15,d13-d00 of this register cannot be written to without first setting reg 2ah bit d2=0 (spdif disabled) and register 28h bit d2=1 (spdif avaliable). 7.5.16. digital audio control (6ah) default: 0000h this read/write register is used to program the digital mixer input status. in the default state, the pcm dac path is enabled and the adc record inputs are dis- abled. the do1 and do0 bits control the input source for the pcm to digital output con- verters. the table describes the available options. 3 0 read & write pre 0 = 0 usec pre-emphasis 1 = pre-emphasis is 50/15 usec 2 0 read & write copy 0 = copyright not asserted 1 = copyright is asserted 1 0 read & write /audio 0 = pcm data 1 = non-audio or non-pcm format 0 0 read & write pro 0 = consumer use of the channel 1 = professional use of the channel d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved do1 do0 bit(s) reset value name description 15:2 0 reserved bits not used, should read back 0 10 do1 spdif digital output source selection: do1 = 0; pcm data from the ac-link to spdif do1 = 1; adc record data to spdif 0 0 do0 always reads zero table 33. digital audio control register bit(s) reset value access name description (note 1-2) table 32. spdif control (continued)
44 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.17. revision code (6ch) default: 0000h the device revision register (index 6ch) contains a software readable revision-spe- cific code used to identify performance, architectural, or software differences between various device revisions. bits 7:0 of the revision register are user read- able; bits 15:8 are not used at this time and will return zeros when read. the lower order bits of the revision register (bits 7:0) are currently set to 00h, and will likely change if there are any stac9766/67 metal revisions. this value can be used by the audio driver, or miniport driver in the case of win98 ? wdm approaches, to adjust software functionality to match the feature-set of the stac9766/67. this will allow the software driver to identify any required operational differences between the existing stac9766/67 and any future versions. 7.5.18. analog special (6eh) default: 0000h the analog special register has several bits used to control various functions spe- cific to the stac9766/67. 7.5.18.1. all mix the ac ? 97 all mix, bit d12 of register 6eh, controls the record source when the stereo mix option is selected for recording. if the ac97 mode is default logic 1, the stereo mix record option will include the sum of the analog sources with or without 3d enhancement, and the main pcm dac output. if the ? all analog record ? option is selected, the stereo mix record option will include the sum of the analog sources only, with or without 3d enhancement. the ? ac ? 97 mode ? is useful for recording all sound sources. the ? all analog ? mode is useful in conjunction with the pop bypass mode for recording all analog sources, which are often further processed and combined with other pcm data to be output directly to the dac out- puts which are configured in pop_bypass mode using the general purpose regis- ter (index 20h). d15 d14 d13 d12 d11 d10 d9 d8 00 00000 0 d7 d6 d5 d4 d3 d2 d1 d0 00 00000 0 d15 d14 d13 d12 d11 d10 d9 d8 reserved ac97 all mix reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved adcslt1 adcslt0 reserved 20/30 sel splyovr en splyovr val
2-9766-d1-6.0-0802 45 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.18.2. adc data on ac link bits d5-d4 select slots for adc data on aclink. 7.5.18.3. mic boost select the mic boost value can be selected with bit d2, which in enabled by register 0eh, bit d6. writing a zero to bit 2 will provide 20db of mic boost. writing a one will pro- vide 30db of mic boost. 7.5.18.4. supply override select the supply override bit, d1, allows override of the supply detect. writing a zero dis- ables the override on supply detect. writing a one, overrides supply detect with bit d0. bit d0 provides the supply override value. a zero forces 3.3v analog operation and one forces 5v analog operation. 7.5.18.5. 72h enable (70h) default: 0000h 7.5.18.6. analog current adjust (72h) default: 0000h the analog current adjust register (index 72h) is a locked register and can only be properly written and read from when abbah has been written into register 70h. the biasx bits allow the analog current to be adjusted with minimal reduction in perfor- mance. a lower analog current setting is not recommended when a 5v analog supply is used. a lower setting for 3.3v supplies is recommended to reduce power consumption for notebook computers to its lowest level. value function 00 left slot 3, right slot 4 01 left slot 7, right slot 8 10 left slot 6, right slot 9 11 left slot 10, right slot 11 table 34. adc data on ac link value function 0 20db 1 30db table 35. mic boost select d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 int apop reserved ibias1 ibias0 rsvd
46 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.18.7. internal power-on/off anti-pop circuit the stac9766/67 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the codec is powered on and off. this function is accomplished by delaying the charge/discharge of the vref capac- itor (pin 27). c vref value of 1uf will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the codec outputs are enabled. the delay will be extended to 30 seconds if a value of c vref value of 10uf is used. the codec outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. the int_apop bit d7 of register 72h allows this delay circuit to be bypassed for rapid production testing. any external component anti-pop circuit is unaffected by the internal circuit. 7.5.19. gpio access register (74h) default: 0800h table 37. gpio access registers (74h) ibias1 ibias0 analog current 0 0 normal current 0 1 80% of nominal analog current 1 0 120% of nominal analog current 1 1 140% of nominal analog current table 36. analog current adjust d15 d14 d13 d12 d11 d10 d9 d8 eapd reserved gpio1 gpio0 eapd_oen reserved gpio1_oen gpio0_oen d7 d6 d5 d4 d3 d2 d1 d0 reserved bit(s) reset value name description 15 0 eapd eapd data output on eapd when bit d11=1 eapd data input from pin when bit d11=0 14 0 reserved reserved 13 0 gpio1 gpio1 data output on gpio1 when bit d9=1 gpio1 data input from pin when bit d9=0 12 0 gpio0 gpio0 data output on gpio0 when bit d8=1 gpio0 data input from pin when bit d8=0 11 1 eapd_oen 0 = eapd data out disabled 1 = eapd data output enabled 10 0 reserved reserved 9 0 gpio1_oen 0 = gpio1 data out disabled 1 = gpio1 data output enabled 8 0 gpio0_oen 0 = gpio0 data out disabled 1 = gpio0 data output enabled 7:0 0 reserved reserved
2-9766-d1-6.0-0802 47 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 the gpio access register requires the output enable bits (d11, d9 and d8) be used in conjunction with the data source selection (input or output) for the eapd, gpio0 and gpio1 (pins 47, 43 and 44 respectively) . for example, to use gpio1 as an output, set d9=1 to enable the output, and use d13 to write the output value desired. to use gpio1 as an input, set d9=0 to disable the output, and use d13 to read the input value. 7.5.20. high pass filter bypass (index 76h and 78h) the high pass filter bypass register (index 78h) is a locked register and can only be properly written and read from when abbah has been written into register 76h. bit d0 controls the high pass filter bypass. default is zero which provides for nor- mal operation where the high pass filter is active. writing a one, will disable, or bypass the adc high pass filter. 7.5.20.1. 78h enable (76h) default: 0000h 7.5.20.2. adc high pass filter bypass(78h) default: 0000h 7.5.21. vendor id1 and id2 (index 7ch and 7eh) these two registers contain four 8-bit id codes. the first three codes have been assigned by microsoft using their plug and play vendor id methodology. the fourth code is a sigmatel, inc. assigned code identifying the stac9766/67. the id1 reg- ister (index 7ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the microsoft id code. the id2 register (index 7eh) contains the value 7666h, which is the third (76h) of the microsoft id code, and 66h which is the stac9766/67 id code. note: the lower half of the vendor id2 register (index 7eh) currently contains the value 66h identifying the stac9766/67. this value can be used by the audio driver, or miniport driver in the case of win98 ? , to adjust software functionality to match the feature-set of the stac9766/67. this portion of the register will likely contain different values if the software profile of the stac9766/67 changes, as in the case of silicon level device modifications. this will allow the software driver to identify any required operational differences between the existing stac9766/67 and any future versions. d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved adc hpf byp
48 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 7.5.21.1. vendor id1 (7ch) default: 8384h 7.5.21.2. vendor id2 7666 (7eh) default: 7666h d15 d14 d13 d12 d11 d10 d9 d8 10 00001 1 d7 d6 d5 d4 d3 d2 d1 d0 10 00010 0 d15 d14 d13 d12 d11 d10 d9 d8 01 11011 0 d7 d6 d5 d4 d3 d2 d1 d0 01 10011 0
2-9766-d1-6.0-0802 49 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 8. low power modes the stac9766/67 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). there are 7 commands of separate power down. the power down options are listed in table 38. the first three bits, pr0..pr2, can be used individually or in combina- tion with each other, and control power distribution to the adc ? s, dac ? s and mixer. the last analog power control bit, pr3, affects analog bias and reference voltages, and can only be used in combination with pr1, pr2, and pr3. pr3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. pr0 and pr1 control the pcm adc ? s and dac ? s only. pr2 and pr3 do not need to be ? set ? before a pr4, but pr0 and pr1 must be ? set ? before pr4. pr5 disables the internal codec clock and requires an external cold reset for recovery. pr6 disables the headphone driver amplifier for additional analog power saving. the figure 19 illustrates one example procedure to do a complete powerdown of stac9766/67. from normal operation, sequential writes to the powerdown register are performed to power down stac9766/67 a piece at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac-link. the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac'97 controller will send an extended pulse on the sync line, issuing a warm reset. this will restart the ac-link (resetting pr4 to zero). the stac9766/ 67 can also be woken up with a cold reset. a cold reset will reset all of the registers to their default states. when a section is powered back on, the powerdown control/ status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. grp bits function pr0 pcm in adc ? s & input mux powerdown pr1 pcm out dacs powerdown pr2 analog mixer powerdown (vref still on) pr3 analog mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (extnl clk off) pr5 internal clk disable pr6 powerdown headphone_out table 38. low power modes figure 19. example of stac9766/67 powerdown/powerup flow warm reset cold reset ready =1 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link default pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 pr0=1 pr1=1 pr2=1 pr4=1
50 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 figure 20 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this configuration can be used when playing a cd (or external line_in source) through stac9766/67 to the speakers, while most of the system in low power mode. the procedure for this fol- lows the previous except that the analog mixer is never shut down. figure 20. stac9766/67 powerdown/powerup flow with analog still alive warm reset normal adcs off pr0 dacs off pr1 digital i/f off pr4 shut off ac-link pr0=0 & adc=1 pr1=0 & dac=1 pr0=1 pr1=1 pr4=1
2-9766-d1-6.0-0802 51 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 9. multiple codec support the stac9766/67 provides support for the multi-codec option according to the intel ac ? 97, rev 2.2 specification. by definition there can be only one primary codec (codec id 00) and up to three secondary codecs (codec ids 01,10, and 11). the codec id functions as a chip select. secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share regis- ters. 9.1. primary/secondary codec selection in a multi-codec environment the codec id is provided by external programming of pins 45 and 46 (cid0 and cid1). the cid pin electrical function is logically inverted from the codec id designation. the corresponding pin state and its associated codec id are listed in the ? codec id selection ? table. also see slot assignment dis- cussion, ? multi-channel programming register (index 74) ? . 9.1.1. primary codec operation as a primary device the stac9766/67 is completely compatible with existing ac'97 definitions and extensions. primary codec registers are accessed exactly as defined in the ac'97 component specification and ac'97 extensions. the stac9766/67 operates as primary by default, and the external id pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. when used as the primary codec, the stac9766/67 generates the master ac-link bit_clk for both the ac'97 digital controller and any secondary codecs. the stac9766/67 can support up to 4, 10 k ? 50 pf loads on the bit_clk. this is to insure that up to 4 codec implementations will not load down the clock output. 9.1.2. secondary codec operation when the stac9766/67 is configured as a secondary device the bit_clk pin is configured as an input at power up. using the bit_clk provided by the primary codec insures that everything on the ac-link will be synchronous. as a secondary device it can be defined as codec id 01, 10, or 11 in the two-bit field(s) of the extended audio and/or extended modem id register(s). cid1 state cid0 state codec id codec status dvdd or floating dvdd or floating 00 primary dvdd or floating 0v 01 secondary 0v dvdd or floating 10 secondary 0v 0v 11 secondary table 39. codec id selection
52 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 9.2. secondary codec register access definitions the ac ? 97 digital controller can independently access primary and secondary codec registers by using a 2-bit codec id field (chip select) which is defined as the lsbs of output slot 0. for secondary codec access, the ac ? 97 digital controller must invalidate the tag bits for slot 1 and 2 command address and data (slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the codec id field (slot 0, bits 1 and 0). as a secondary codec, the stac9766/67 will disregard the command address and command data (slot 0, bits 14 and 13) tag bits when it sees a 2-bit codec id value (slot 0, bits 1 and 0) that matches its configuration. in a sense the secondary codec id field functions as an alternative valid command address (for secondary reads and writes) and command data (for secondary writes) tag indicator. secondary codecs must monitor the frame valid bit, and ignore the frame (regard- less of the state of the secondary codec id bits) if it is not valid. ac ? 97 digital con- trollers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set. this method is designed to be backward compatible with existing ac ? 97 controllers and codecs. there is no change to output slot 1 or 2 definitions. output tag slot (16-bits) bit description 15 frame valid 14 slot 1 valid command address bit ( ? primary codec only) 13 slot 2 valid command data bit ( ? primary codec only) 12-3 slot 3-12 valid bits as defined by ac'97 2 reserved (set to ? 0 ? ) ? 1-0 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary) note: ? new definitions for secondary codec register access table 40. secondary codec register access slot 0 bit definitions
2-9766-d1-6.0-0802 53 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 10. testability the stac9766/67 has two test modes. one is for ate in-circuit test and the other is restricted for sigmatel ? s internal use. stac9766/67 enters the ate in circuit test mode if sdata_out is sampled high at the trailing edge of reset#. once in the ate test mode, the digital ac-link outputs (bit_clk and sdata_in) are driven to a high impedance state. this allows ate in-circuit testing of the ac'97 controller. use of the ate test mode is the recommended means of removing the codec from the ac-link when another codec is to be used as the primary. this case will never occur during standard operating conditions. once either of the two test modes have been entered, the stac9766/67 must be issued another reset# with all ac-link signals held low to return to the normal operating mode.
54 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 11. pin description dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 dvdd2 9 sync 10 reset# 11 pc_beep 12 24 line_in_r 23 line_in_l 22 mic2 21 mic1 20 cd_r 19 cd_gnd 18 cd_l 17 video_r 16 video_l 15 aux_r 14 aux_l 13 phone 36 line_out_r 35 line_out_l 34 nc 33 nc 32 cap2 31 nc 30 afilt2 29 afilt1 28 vrefout 27 vref 26 avss1 25 avdd1 mono_out 37 avdd2 38 hp_out_l 39 hp_comm 40 hp_out_r 41 avss2 42 gpio0 43 gpio1 44 cid0 45 cid1 46 eapd 47 spdif 48 figure 21. stac9766/67 pin description drawing pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating. 48-pin tqfp
2-9766-d1-6.0-0802 55 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 11.1. digital i/o these signals connect the stac9766/67 to its ac ? 97 controller counterpart, an external crystal, multi-codec selection and external audio amplifier. pin name pin # type description xtl_in 2 i 24.576 mhz crystal or external clock source xtl_out 3 i/o 24.576 mhz crystal or ground if external clock source connected to xtal_in sdata_out 5 i serial, time division multiplexed, ac ? 97 input stream bit_clk 6 i/o 12.288 mhz serial data clock sdata__in 8 o serial, time division multiplexed, ac ? 97 output stream sync 10 i 48 khz fixed rate sample sync reset# 11 i ac ? 97 master h/w reset nc 31 i/o no connect nc 33 i/o no connect nc 34 i/o no connect gpio0 43 i/o general purpose i/o gpio1 44 i/o general purpose i/o cid0 45 i multi-codec id select ? bit 0 cid1 46 i multi-codec id select ? bit 1 eapd 47 i/o external amplifier power down spdif 48 o spdif digital output pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating. table 41. digital connection signals
56 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 11.2. analog i/o these signals connect the stac9766/67 to analog sources and sinks, including microphones and speakers. note: * any unused input pins should be tied together through a capacitor (0.1 f suggested) to ground, except the mic inputs which should have their own capacitor to ground if not used. pin name pin # type description pc-beep 12 i* pc speaker beep pass-through phone 13 i* from telephony subsystem speakerphone (or dlp:down line phone) aux_l 14 i* aux left channel aux_r 15 i* aux right channel video_l 16 i* video audio left channel video_r 17 i* video audio right channel cd_l 18 i* cd audio left channel cd_gnd 19 i* cd audio analog ground cd_r 20 i* cd audio right channel mic1 21 i* desktop microphone input mic2 22 i* second microphone input line_in_l 23 i* line in left channel line_in_r 24 i* line in right channel line_out_l 35 o line out left channel line_out_r 36 o line out right channel mono_out 37 o to telephony subsystem speakerphone(or dlp ? down line phone) hp_out_l 39 o headphone out left channel hp_comm 40 o headphone ground return hp_out_r 41 o headphone out right channel table 42. analog connection signals
2-9766-d1-6.0-0802 57 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 11.3. filter/references/gpio these signals are connected to resistors, capacitors, specific voltages, or provide general purpose i/o. 11.4. power and ground signals signal name pin number type description vref 27 o analog ground (.45*vdd, at 5v; .41*vdd at 3v) vrefout 28 o reference voltage out 5ma drive (intended for mic bias) (~vdd/2) afilt1 29 o anti-aliasing filter cap - adc left channel afilt2 30 o anti-aliasing filter cap - adc right channel cap2 32 o adc reference cap table 43. filtering and voltage references pin name pin # type description avdd1 25 i analog vdd = 5.0v or 3.3v avdd2 38 i analog vdd = 5.0v or 3.3v (headphone power source) avss1 26 i analog gnd avss2 42 i analog gnd dvdd1 1 i digital vdd = 3.3v dvdd2 9 i digital vdd = 3.3v dvss1 4 i digital gnd dvss2 7 i digital gnd table 44. power and ground signals
58 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 12. package drawing key tqfp dimensions d9.00 mm d1 7.00 mm e9.00 mm e1 7.00 mm a (lead width) 0.20 mm e (pitch) 0.50 mm thickness 1.4 mm table 45. 48-pin tqfp package dimensions 48 pin tqfp a d1 d e e1 e 38 26 14 2 figure 23. 48-pin tqfp package drawing
2-9766-d1-6.0-0802 59 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 13. appendix a: split independent power supply operation in pc applications, one power supply input to the stac9766/67 may be derived from a supply regulator (as shown in figure 24) and the other directly from the pci power supply bus. when power is applied to the pc, the regulated supply input to the ic will be applied some time delay after the pci power supply. without proper on-chip partitioning of the analog and digital circuitry, some manufacturer ? s codecs would be subject to on-chip scr type latch-up. sigmatel ? s stac9766/67 specifically allows power-up sequencing delays between the analog (avddx) and digital (vdddx) supply pins. these two power supplies can power-up independently and at different rates with no adverse effects to the codec. the ic is designed with independent analog and digital circuitry that prevents on-chip scr type latch-up.
60 2-9766-d1-6.0-0802 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f *suggested avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 32 *optional 0.1 f 1 f* 820 pf 29 30 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 line_out_r 35 line_out_l 43 44 40 48 34 33 31 0.1 f 1 f* 27 vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter 3.3v 5% 3.3v or 5v 5% optional *optional cap2 afilt1 afilt2 gpio0 gpio1 hp_comm spdif nc nc nc vref sdata_in stac9766 figure 24. stac9766/67 split independent power supply operation typical connection diagram pin 48: to enable spdif, use an 1k-10k external pulldown. to disable spdif, use an 1k-10k external pullup. do not leave pin 48 floating.
2-9766-d1-6.0-0802 61 stac9766/67 two-channel ac ? 97 codecs with headphone drive and spdif output not recommended for new designs - 8/2/02 14. appendix b: programming registers note: 1. all registers not shown and those labeled ? reserved ? can be written to but are don ? t care upon read back. 2. pc_beep default to 0000h, mute off. reg #name d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0default 00h reset rsrvd se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6990h 02h master volume mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 reserved mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h hp_out mixer volume mute rsrvd hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 reserved hpr5 hpr4 hpr3 hpr2 hpr1 hpr0 8000h 06h master volume mono mute reserved mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute reserved pv3 pv2 pv1 pv0 rsrvd 0000h 0ch phone volume mute reserved gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute reserved boosted rsrvd gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 1ah record select reserved sl2 sl1 sl0 reserved sr2 sr1 sr0 0000h 1ch record gain mute reserved gl3 gl2 gl1 gl0 reserved gr3 gr2 gr1 gr0 8000h 20h general purpose pop byp rsrvd 3d reserved mix ms lpbk reserved 0000h 22h 3d control reserved dp3 dp2 reserved 0000h 24h reserved reserved 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 reserved ref anl dac adc 000fh 28h extended audio id id1 id0 reserved rev1 (0) rev0 (1) amap ldac sdac cdac dsa1 dsa0 rsvd spdif dra vra 0605h 2ah extended audio control/ status reserved spcv rsrvd spsa1 spsa0 rsrvd spdif rsrvd vra enable 0400h 2ch pcm dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm lr adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 3ah spdif control #v drs spsr1 spsr2 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy #pcm/ audio pro 2a00h 60h z_data volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 6ah digital audio control reserved do1 do0 0000h 6ch revision code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 6eh analog special reserved ac97 all mix reserved adcslot 1 adcslot 0 rsvd mic gain va lue sply ovr en sply ovr val 1000h 70h 72h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 72h analog current adjust reserved i n t apop reserved ibias<1:0> rsvd 0000h 74h gpio access eapd reser ved gpio1 gpio0 eapd_ oen reser ved gpio1_ oen gpio0_ oen reserved 0000h 76h 78h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 78h high pass filter bypass rseserved adc hpf byp 0000h 7chvendor id11000001110000100 8384h 7eh vendor id2 9766 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 7666h

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